Benchmark pages of AIDA64 Extreme provide several methods to measure system performance. These benchmarks are synthetic, so their results show only the theoretical (maximum) performance of the system. CPU and FPU benchmarks of AIDA64 Extreme are built on the multi-threaded AIDA64 Benchmark Engine that supports up to 1280 simultaneous processing threads. It also supports multi-processor, multi-core and HyperThreading enabled systems.

Ray tracing benchmarks

These benchmarks measure the single and double precision (also known as 32-bit and 64-bit) floating-point performance through the computation of a scene with a SIMD-enhanced ray tracing engine. The code behind this benchmark method is written in Assembly, and it is extremely optimized for every popular AMD, Intel and VIA processor core variants by utilizing the appropriate x87, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, XOP, FMA, FMA4 and AVX-512 instruction set extension. Both FP32 and FP64 Ray-Trace test is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

Memory Tests

Memory bandwidth benchmarks (Memory Read, Memory Write, Memory Copy) measure the maximum achievable memory data transfer bandwidth. The code behind these benchmark methods are written in Assembly and they are extremely optimized for every popular AMD, Intel and VIA processor achieveablecore variants by utilizing the appropriate x86/x64, x87, MMX, MMX+, 3DNow!, SSE, SSE2, SSE4.1, AVX, AVX2 and AVX-512 instruction set extension. The Memory Latency benchmark measures the typical delay when the CPU reads data from system memory. Memory latency time means the penalty measured from the issuing of the read command until the data arrives to the integer registers of the CPU.

CheckMate Benchmark

This integer benchmark focuses on the branch prediction capabilities and the misprediction penalties of the CPU. It finds the solutions for the classic "Queens problem" on a 16x16 chessboard. At the same clock speed, theoretically, the processor with the shorter pipeline and smaller misprediction penalties will attain higher benchmark scores. The CheckMate benchmark uses integer MMX, SSE2, SSSE3, AVX, AVX2, and AVX512 optimizations to ensure comprehensive performance testing. Additionally, it scales much better for multi-core CPUs than the previous Queen benchmark, taking full advantage of modern processors' parallel processing capabilities.

CPU PhotoWorxx Benchmark

This benchmark performs different common tasks used during digital photo processing. It performs the following tasks on a very large RGB image:

• Fill the image with random colored pixels
• Rotate 90 degrees CCW
• Rotate 180 degrees
• Difference
• Color space conversion (used e.g. during JPEG conversion)

This benchmark stresses the SIMD integer arithmetic execution units of the CPU and also the memory subsystem. CPU PhotoWorxx test uses the appropriate x87, MMX, MMX+, 3DNow!, 3DNow!+, SSE, SSE2, SSSE3, SSE4.1, SSE4A, AVX, AVX2, XOP and AVX-512 instruction set extension and it is NUMA, HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

CPU ZLib Benchmark

This integer benchmark measures combined CPU and memory subsystem performance through the public ZLib compression library. CPU ZLib test uses only the basic x86 instructions, and it is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

CPU AES Benchmark

This benchmark measures CPU performance using AES (Advanced Encryption Standard) data encryption. In cryptography AES is a symmetric-key encryption standard. AES is used in several compression tools today, like 7z, RAR, WinZip, and also in disk encryption solutions like BitLocker, FileVault (Mac OS X), TrueCrypt. CPU AES test uses the appropriate x86, MMX and SSE4.1 instructions, and it's hardware accelerated on VIA PadLock Security Engine capable VIA C3, VIA C7, VIA Nano and VIA QuadCore processors; and on Intel AES-NI instruction set extension and the future VAES capable processors. The test is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

CPU SHA3 Benchmark

This integer benchmark measures CPU performance using the SHA3-512 hashing algorithm defined in the Federal Information Processing Standards Publication 202 (https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.202.pdf).  The code behind this benchmark method is written in Assembly, and it is optimized for every popular AMD, Intel and VIA processor core variants by utilizing the appropriate MMX, SSE2, AVX, AVX2, AVX-512, XOP, and BMI2 instruction set extension.

In this benchmark, every thread is working on independent 8 KB data blocks.
 

FPU Julia Benchmark

This benchmark measures the single precision (also known as 32-bit) floating-point performance through the computation of several frames of the popular "Julia" fractal. The code behind this benchmark method is written in Assembly, and it is extremely optimized for every popular AMD, Intel and VIA processor core variants by utilizing the appropriate x87, 3DNow!, 3DNow!+, SSE, AVX, AVX2, FMA, FMA4 and AVX-512 instruction set extension. FPU Julia test is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

FPU Mandel Benchmark

This benchmark measures the double precision (also known as 64-bit) floating-point performance through the computation of several frames of the popular "Mandelbrot" fractal. The code behind this benchmark method is written in Assembly, and it is extremely optimized for every popular AMD, Intel and VIA processor core variants by utilizing the appropriate x87, SSE2, AVX, AVX2, FMA, FMA4 and AVX-512 instruction set extension. FPU Mandel test is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.

FPU SinJulia Benchmark

This benchmark measures the extended precision (also known as 80-bit) floating-point performance through the computation of a single frame of a modified "Julia" fractal. The code behind this benchmark method is written in Assembly, and it is extremely optimized for every popular AMD, Intel and VIA processor core variants by utilizing trigonometric and exponential x87 instructions. FPU SinJulia is HyperThreading, multi-processor (SMP) and multi-core (CMP) aware.